1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to a dynamic random access memory (DRAM).
2. Description of the Related Art
Most DRAM cells put in practice in these days each comprise an (insulating gate type) MOS transistor serving as a transfer gate and connected to a word line and to a bit line, and a capacitor connected to the MOS transistor for storing data.
To more highly integrate DRAM cells to thereby reduce the cost of each bit, the inventor of the invention has proposed, in U.S. application Ser. No. 687,687, cascade gate type semiconductor memory cells shown in FIGS. 1 and 2.
The DRAM cell shown in FIG. 1 comprises MOS transistors Q1-Q4 connected by cascade connection, and capacitors C1-C4 each having one end connected to one end of the corresponding transistor Q1-Q4, for storing data. By turning on and off the transistors Q1-Q4 in a predetermined order, data items are successively read to a read-out/write-in node 1 which is connected to a bit line BL from the capacitors C1, C2, C3, and C4 in the order mentioned, i.e., in the order from the capacitor closest to the bit line BL to that remotest therefrom. Similarly, the read-out write-in data items are written from the node 1 into the capacitors C4, C3, C2, and C1 in the order mentioned, i.e., in the order of from the capacitor remotest from the bit line BL to that closest thereto.
The DRAM cell shown in FIG. 2 is similar to that shown in FIG. 1 except that it further incorporates a second node N2 and a MOS transistor Q5 connected between the transistor Q4 and the second node N2. Also in the DRAM cell of FIG. 2, by turning on and off the transistors Q1-Q5 in a predetermined order, data items are successively read to the node 1 from the capacitors C1, C2, C3, and C4 in the order mentioned, and the read-out/write-in data items are written from the node 2 into the capacitors C1, C2, C3, and C4 in the order mentioned.
The above-described cascade gate type memory cells shown in FIGS. 1 and 2 can store data of a plurality of bits in units of one bit. Thus, as compared with a conventional DRAM consisting of an array of cells each having a transistor and a capacitor, a remarkably highly integrated DRAM can be formed of an array of memory cells of the cascade gate type, thereby much reducing the cost of one cell or bit, since only one contact is required in the latter case to connect a plurality of cells or bits to a bit line.
In the DRAM made of cascade gate type memory cells, however, data stored in each cell is read out in a destructive read out manner, so that it is always needed to rewrite data into the cell. But, rewriting new data into any capacitor cannot be performed immediately after the stored data is read out, since in any memory cell of the cascade gate type, the order of the capacitors from which the stored data is read out is predetermined. That is, rewriting can be performed for the first time after data stored in all the capacitors are read out completely.
Thus, the DRAM comprising of a cascade gate type memory cell array must have means for rewriting (or writing) data in order into the capacitors employed in each cell, after data of a plurality of bits are read out of the cell.